Get A Designer’s Guide to Built-In Self-Test PDF

By Charles E. Stroud

ISBN-10: 0306475049

ISBN-13: 9780306475047

ISBN-10: 1402070500

ISBN-13: 9781402070501

A fresh technological boost is the artwork of designing circuits to check themselves, known as a integrated Self-Test (BIST). this concept used to be first proposed round 1980 and has grown to develop into some of the most very important checking out suggestions on the present time, in addition to for the long run. This e-book is written from a designer's standpoint and describes the foremost BIST techniques which were proposed and applied considering 1980, besides their benefits and barriers. The BIST methods contain the integrated common sense Block Observer, pseudo-exhaustive BIST concepts, round BIST, scan-based BIST, BIST for normal buildings, BIST for FPGAs and CPLDs, mixed-signal BIST, and the combination of BIST with concurrent fault detection suggestions for online trying out. specific consciousness is paid to system-level use of BIST with the intention to maximize the advantages of BIST via diminished checking out time and value in addition to excessive diagnostic answer. the writer spent 15 years as a fashion designer at Bell Labs the place he designed over 20 creation VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of varied forms for normal buildings and normal sequential common sense, together with the 1st BIST for Random entry thoughts (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the previous 10 years in academia the place his examine and improvement maintains to target BIST, together with the 1st BIST for FPGAs and CPLDs in addition to endured paintings within the region of BIST for normal sequential common sense and mixed-signal structures. He holds 10 US patents (with five extra pending) for varied varieties of BIST techniques. accordingly, the writer brings a special mixture of data and adventure to this functional advisor for designers, try engineers, product engineers, approach diagnosticians, and managers.

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Extra info for A Designer’s Guide to Built-In Self-Test

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Fault Models and Detection Realistic potential bridging fault sites can be accurately extracted from the physical design by using existing CAD tools developed for capacitance extraction from the physical design database for post-layout timing simulations [164]. By extracting fringe capacitance we determine potential bridging faults on a given mask layer. Extracting overlap capacitance, on the other hand, yields potential bridging faults between mask layers. Using the parallel plate model, overlap capacitance is given by: where A is the area of overlap and d is the distance between the two conductors is the inter-layer dielectric constant).

An Overview of BIST 9 Chapter 1. An Overview of BIST (BIST Done) that the BIST sequence is complete and that the BIST results are valid and can be read to determine the fault-free/faulty status of the CUT. 2 A Simple BIST Design As an example of a BIST implementation, assume that a set of test vectors has already been developed for the CUT and we want to use those test vectors to test the CUT during the BIST sequence. 5. This combination of counter and ROM would constitute the TPG function in the BIST circuitry.

While this sequence results in a total of 6 test vectors to detect these four faults, the set of test vectors can be minimized to the sequence {00, 10, 00, 01} for the single fault model. The first ‘00’ test vector sets up the necessary logic 1 at the gate output. The ‘10’ test vector then detects the A NFET stuck-off and sets up a logic 0 at the gate output if the A NFET stuck-off fault is not present. The second ‘00’ test vector detects the A and B PFETs stuck-off and sets up a logic 1 at the gate output if neither PFET stuck-off fault is present.

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A Designer’s Guide to Built-In Self-Test by Charles E. Stroud

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